Display system and driving device thereof

ABSTRACT

A display system includes a light emitting array and a driving device. The light emitting array includes multiple scan lines, multiple drive lines and multiple light emitting elements. The driving device includes a controller, a charge balance line and a charge sharing circuit. The controller generates a control output. The charge sharing circuit is coupled to the drive lines, the charge balance line and the controller, and receives the control output from the controller. With respect to each of the drive lines, the charge sharing circuit is operable, based on the control output, to establish or not establish an electrical connection between the drive line and the charge balance line.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of Taiwanese Patent Application No.110113793, filed on Apr. 16, 2021.

FIELD

The disclosure relates to display techniques, and more particularly to adisplay system and a driving device thereof.

BACKGROUND

Alight emitting diode (LED) array includes multiple scan lines, multipledrive lines and multiple LEDs, and is driven by a driving device to emitlight in a line scan manner. For each line of the line scan of the LEDarray, if the LEDs in the line are set to have the same expectedbrightness level, since respective voltages across the LEDs in the lineare different before the LEDs in the line become conducting, the LEDs inthe line would become conducting at different time points, so respectiveconduction periods of the LEDs in the line would be different in length,and respective actual brightness levels of the LEDs in the line would bedifferent. When the expected brightness level of the LEDs in the line islow, the aforesaid problem is even more serious since the conductionperiods of the LEDs in the line are short in length and lengthdifferences among the conduction periods of the LEDs in the line aremore noticeable.

SUMMARY

Therefore, an object of the disclosure is to provide a display systemand a driving device thereof. The display system can alleviate thedrawback of the prior art.

According to an aspect of the disclosure, the display system includes alight emitting array and a driving device. The light emitting arrayincludes a plurality of scan lines, a plurality of drive lines and aplurality of light emitting elements. The light emitting elements arearranged in a matrix that has a plurality of rows respectivelycorresponding to the scan lines and a plurality of columns respectivelycorresponding to the drive lines. Each of the light emitting elementshas a first terminal and a second terminal. With respect to each of therows, the first terminals of the light emitting elements in the row areconnected to the scan line corresponding to the row. With respect toeach of the columns, the second terminals of the light emitting elementsin the column are connected to the drive line corresponding to thecolumn. The driving device includes a controller, a charge balance lineand a charge sharing circuit. The controller generates a control output.The charge sharing circuit is coupled to the drive lines, the chargebalance line and the controller, and receives the control output fromthe controller. With respect to each of the drive lines, the chargesharing circuit is operable, based on the control output, to establishor not establish an electrical connection between the drive line and thecharge balance line.

According to another aspect of the disclosure, the driving device isoperatively associated with a light emitting array. The light emittingarray includes a plurality of scan lines, a plurality of drive lines anda plurality of light emitting elements. The light emitting elements arearranged in a matrix that has a plurality of rows respectivelycorresponding to the scan lines and a plurality of columns respectivelycorresponding to the drive lines. Each of the light emitting elementshas a first terminal and a second terminal. With respect to each of therows, the first terminals of the light emitting elements in the row areconnected to the scan line corresponding to the row. With respect toeach of the columns, the second terminals of the light emitting elementsin the column are connected to the drive line corresponding to thecolumn. The driving device includes a controller, a charge balance lineand a charge sharing circuit. The controller generates a control output.The charge sharing circuit is adapted to be coupled to the drive lines,is further coupled to the charge balance line and the controller, andreceives the control output from the controller. With respect to each ofthe drive lines, the charge sharing circuit is operable, based on thecontrol output, to establish or not establish an electrical connectionbetween the drive line and the charge balance line.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the disclosure will become apparent inthe following detailed description of the embodiment with reference tothe accompanying drawings, of which:

FIG. 1 is a circuit block diagram illustrating an embodiment of adisplay system according to the disclosure;

FIG. 2 is a circuit block diagram illustrating a driver of theembodiment;

FIG. 3 is a circuit block diagram illustrating a first implementation ofthe embodiment;

FIG. 4 is a timing diagram illustrating operations of the firstimplementation;

FIG. 5 is a circuit block diagram illustrating a second implementationof the embodiment; and

FIGS. 6 and 7 are timing diagrams illustrating operations of the secondimplementation.

DETAILED DESCRIPTION

Referring to FIGS. 1 and 2, an embodiment of a display system accordingto the disclosure includes a light emitting array 1 and a driving device5.

The light emitting array 1 includes a plurality of scan lines 2, aplurality of drive lines 3 and a plurality of light emitting elements 4.The light emitting elements 4 are arranged in a matrix that has aplurality of rows respectively corresponding to the scan lines 2 and aplurality of columns respectively corresponding to the drive lines 3.Each of the light emitting elements 4 has a first terminal 41 and asecond terminal 42. With respect to each of the rows, the firstterminals 41 of the light emitting elements 4 in the row are connectedto the scan line 2 corresponding to the row. With respect to each of thecolumns, the second terminals 42 of the light emitting elements 4 in thecolumn are connected to the drive line 3 corresponding to the column. Inthis embodiment, each of the light emitting elements 4 is a lightemitting diode (LED) having an anode and a cathode that respectivelyserve as the first terminal 41 and the second terminal 42 of the lightemitting element 4.

The driving device 5 includes a controller 51, a charge balance line 52,a charge sharing circuit 53, a driver 54 and a scan selector 55.

The controller 51 generates a control output including at least onecontrol signal, a pulse width modulation output including at least onepulse width modulation signal, and an enable signal.

The charge sharing circuit 53 is coupled to the drive lines 3, thecharge balance line 52 and the controller 51, and receives the controloutput from the controller 51. With respect to each of the drive lines3, the charge sharing circuit 53 is operable, based on the controloutput, to establish or not establish an electrical connection betweenthe drive line 3 and the charge balance line 52.

In this embodiment, the charge sharing circuit 53 includes a pluralityof balance switches 531 respectively corresponding to the drive lines 3.With respect to each of the drive lines 3, the balance switch 531corresponding to the drive line 3 is coupled between the drive line 3and the charge balance line 52, establishes the electrical connectionbetween the drive line 3 and the charge balance line 52 when conducting,and does not establish the electrical connection between the drive line3 and the charge balance line 52 when not conducting. Switching of thebalance switches 531 between conduction and non-conduction is dependenton the control output.

The driver 54 is coupled to the drive lines 3 and the controller 51, andreceives the pulse width modulation output and the enable signal fromthe controller 51. Based on the pulse width modulation output, thedriver 54 is operable to provide or not to provide respectively to thedrive lines 3 a plurality of drive currents respectively correspondingto the drive lines 3. Based on the enable signal, the driver 54 isoperable to provide or not to provide respectively to the drive lines 3a plurality of bias voltages respectively corresponding to the drivelines 3.

In this embodiment, the driver 54 includes a plurality of drive switches541 respectively corresponding to the drive lines 3, a plurality ofcurrent sources 542 respectively corresponding to the drive lines 3, anda bias circuit 543. With respect to each of the drive lines 3, thecorresponding drive switch 541 and the corresponding current source 542are coupled in series between the drive line 3 and ground, with thecorresponding drive switch 541 coupled to ground and the correspondingcurrent source 542 coupled to the drive line 3; when the correspondingdrive switch 541 conducts, the corresponding current source 542 providesto the drive line 3 the drive current that corresponds to the drive line3 and that has a fixed magnitude; and when the corresponding driveswitch 541 does not conduct, the corresponding current source 542 doesnot provide the corresponding drive current to the drive line 3.Switching of the drive switches 541 between conduction andnon-conduction is dependent on the pulse width modulation output.

Referring to FIG. 3, the bias circuit 543 is coupled to the drive lines3 and the controller 51, and receives the enable signal (EN) from thecontroller 51. Based on the enable signal (EN), the bias circuit 543 isoperable to provide or not to provide the bias voltages respectively tothe drive lines 3.

In this embodiment, the bias circuit 543 includes a plurality of biasswitches 544 respectively corresponding to the drive lines 3, and aplurality of voltage sources 545 respectively corresponding to the drivelines 3. With respect to each of the drive lines 3, the correspondingbias switch 544 is coupled between the drive line 3 and thecorresponding voltage source 545, is further coupled to the controller51 to receive the enable signal (EN), and switches between conductionand non-conduction based on the enable signal (EN); when the bias switch544 conducts, the voltage source 545 provides the corresponding biasvoltage to the drive line 3; and when the bias switch 544 does notconduct, the voltage source 545 does not provide the bias voltage to thedrive line 3. Magnitudes of the bias voltages are set to be equal to oneof a first voltage level and a second voltage level.

Referring back to FIGS. 1 and 2, the scan selector 55 is coupled to thescan lines 2, is to receive an input voltage (Vin), and outputs theinput voltage (Vin) to the scan lines 2 sequentially without overlappingin time so as to drive the light emitting elements 4 to emit light in aline scan manner.

In this embodiment, the first voltage level is sufficient to causenon-conduction of the light emitting elements 4 in the row thatcorresponds to the scan line 2 supplied with the input voltage (Vin)(hereinafter referred to as the target light emitting elements 4), andis used to eliminate ghost phenomenon of the light emitting array 1. Thesecond voltage level is smaller than the first voltage level, and issufficient to cause a voltage across each of the target light emittingelements 4 to be smaller than but close to a conduction voltage of thelight emitting element 4 in magnitude.

Referring to FIGS. 3 and 4, FIG. 3 illustrates a first implementation ofthis embodiment, and FIG. 4 illustrates operations of the firstimplementation. For convenience of explanation, there are three drivelines 3 in the first implementation, and only one of the scan lines 2and the corresponding one row of the light emitting elements 4 aredepicted in FIG. 3. In the first implementation, the control outputincludes a control signal (CTRL); the pulse width modulation outputincludes a pulse width modulation signal (PWM); each of the balanceswitches 531 is coupled to the controller 51 to receive the controlsignal (CTRL), and switches between conduction and non-conduction basedon the control signal (CTRL); and each of the drive switches 541 iscoupled to the controller 51 to receive the pulse width modulationsignal (PWM), and switches between conduction and non-conduction basedon the pulse width modulation signal (PWM). In other words, the balanceswitches 531 switch between conduction and non-conduction synchronously,and the drive switches 541 switch between conduction and non-conductionsynchronously.

During each line scan cycle of the light emitting elements 4, thedriving device 5 sequentially operates in a first phase (I), a secondphase (II), a third phase (III) and a fourth phase (IV).

In the first phase (I) from time t0 to time t1, the enable signal (EN)is at an active logic level (e.g., a logic high level) corresponding toconduction of the bias switches 544; the control signal (CTRL) is at aninactive logic level (e.g., a logic low level) corresponding tonon-conduction of the balance switches 531; the pulse width modulationsignal (PWM) is at an inactive logic level (e.g., a logic low level)corresponding to non-conduction of the drive switches 541; with respectto each of the drive lines 3, the corresponding voltage source 545provides the corresponding bias voltage to the drive line 3; and themagnitudes of the bias voltages respectively provided by the voltagesources 545 are set to be equal to the first voltage level (L1).Therefore, magnitudes of voltages (VDX1-VDX3) respectively at the drivelines 3 are forced to be equal to the first voltage level (L1),resulting in non-conduction of the target light emitting elements 4.

In the second phase (II) from time t1 to time t2, the enable signal (EN)is at the active logic level (i.e., the logic high level) correspondingto conduction of the bias switches 544; the control signal (CTRL) is atthe inactive logic level (i.e., the logic low level) corresponding tonon-conduction of the balance switches 531; the pulse width modulationsignal (PWM) is at the inactive logic level (i.e., the logic low level)corresponding to non-conduction of the drive switches 541; with respectto each of the drive lines 3, the corresponding voltage source 545provides the corresponding bias voltage to the drive line 3; and themagnitudes of the bias voltages respectively provided by the voltagesources 545 are set to be equal to the second voltage level (L2).Therefore, the magnitudes of the voltages (VDX1-VDX3) are forced to besubstantially equal to the second voltage level (L2), the target lightemitting elements 4 remain non-conducting, and the voltage across eachof the target light emitting elements 4 is smaller than but close to theconduction voltage of the target light emitting element 4 in magnitude.It should be noted that the magnitudes of the voltages (VDX1-VDX3) maybe different from each other because of non-ideal effects of the lightemitting array 1 (see FIG. 1).

As shown in FIG. 4, when the pulse width modulation signal (PWM) has aduty cycle greater than 0% and smaller than 100%, the third phase (III)from time t2 to time t4 is divided into a former portion from time t2 totime t3 and a latter portion from time t3 to time t4. The third phase(III) has a fixed time span, and the latter portion has a time spanpositively correlated to the duty cycle of the pulse width modulationsignal (PWM). In the former portion, the enable signal (EN) is at aninactive logic level (e.g., a logic low level) corresponding tonon-conduction of the bias switches 544; the control signal (CTRL) is atan active logic level (e.g., a logic high level) corresponding toconduction of the balance switches 531; the pulse width modulationsignal (PWM) is at the inactive logic level (i.e., the logic low level)corresponding to non-conduction of the drive switches 541; and the drivelines 3 are coupled to the charge balance line 52. Therefore, themagnitude differences among the voltages (VDX1-VDX3) gradually decreasebecause of charge sharing among the drive lines 3. In the latterportion, the enable signal (EN) is at the inactive logic level (i.e.,the logic low level) corresponding to non-conduction of the biasswitches 544; the control signal (CTRL) is at the inactive logic level(i.e., the logic low level) corresponding to non-conduction of thebalance switches 531; the pulse width modulation signal (PWM) is at anactive logic level (e.g., a logic high level) corresponding toconduction of the drive switches 541; and with respective to each of thedrive lines 3, the corresponding current source 542 provides thecorresponding drive current to the drive line 3. Therefore, themagnitudes of the voltages (VDX1-VDX3) drop, and the target lightemitting elements 4 become conducting.

It should be noted that the third phase (III) would only have the formerportion when the duty cycle of the pulse width modulation signal (PWM)is 0%, and would only have the latter portion when the duty cycle of thepulse width modulation signal (PWM) is 100%.

In the fourth phase (IV) from time t4 to time t5, the enable signal (EN)is at the inactive logic level (i.e., the logic low level) correspondingto non-conduction of the bias switches 544; the control signal (CTRL) isat the inactive logic level (i.e., the logic low level) corresponding tonon-conduction of the balance switches 531; and the pulse widthmodulation signal (PWM) is at the inactive logic level (i.e., the logiclow level) corresponding to non-conduction of the drive switches 541.

Referring to FIGS. 5 to 7, FIG. 5 illustrates a second implementation ofthis embodiment, and FIGS. 6 and 7 illustrate operations of the secondimplementation. For convenience of explanation, there are three drivelines 3 in the second implementation, and only one of the scan lines 2and the corresponding one row of the light emitting elements 4 aredepicted in FIG. 5. In the second implementation, the control outputincludes a plurality of control signals (e.g., three control signals(CTRL1-CTRL3)) respectively corresponding to the drive lines 3; thepulse width modulation output includes a plurality of pulse widthmodulation signals (e.g., three pulse width modulation signals(PWM1-PWM3)) respectively corresponding to the drive lines 3; and withrespect to each of the drive lines 3, the corresponding balance switch531 is coupled to the controller 51 to receive the corresponding controlsignal (CTRL1/CTRL2/CTRL3), and switches between conduction andnon-conduction based on the corresponding control signal(CTRL1/CTRL2/CTRL3), and the corresponding drive switch 541 is coupledto the controller 51 to receive the corresponding pulse width modulationsignal (PWM1/PWM2/PWM3), and switches between conduction andnon-conduction based on the corresponding pulse width modulation signal(PWM1/PWM2/PWM3).

During each line scan cycle of the light emitting elements 4, thedriving device 5 sequentially operates in a first phase (I), a secondphase (II), a third phase (III) and a fourth phase (IV).

In the first phase (I) from time t0 to time t1, the enable signal (EN)is at an active logic level (e.g., a logic high level) corresponding toconduction of the bias switches 544; each of the control signals(CTRL1-CTRL3) is at an inactive logic level (e.g., a logic low level)corresponding to non-conduction of the corresponding balance switch 531;each of the pulse width modulation signals (PWM1-PWM3) is at an inactivelogic level (e.g., a logic low level) corresponding to non-conduction ofthe corresponding drive switch 541;

with respect to each of the drive lines 3, the corresponding voltagesource 545 provides the corresponding bias voltage to the drive line 3;and the magnitudes of the bias voltages respectively provided by thevoltage sources 545 are set to be equal to the first voltage level (L1).Therefore, magnitudes of voltages (VDX1-VDX3) respectively at the drivelines 3 are forced to be equal to the first voltage level (L1),resulting in non-conduction of the target light emitting elements 4.

In the second phase (II) from time t1 to time t2, the enable signal (EN)is at the active logic level (i.e., the logic high level) correspondingto conduction of the bias switches 544; each of the control signals(CTRL1-CTRL3) is at the inactive logic level (i.e., the logic low level)corresponding to non-conduction of the corresponding balance switch 531;each of the pulse width modulation signals (PWM1-PWM3) is at theinactive logic level (i.e., the logic low level) corresponding tonon-conduction of the corresponding drive switch 541; with respect toeach of the drive lines 3, the corresponding voltage source 545 providesthe corresponding bias voltage to the drive line 3; and the magnitudesof the bias voltages respectively provided by the voltage sources 545are set to be equal to the second voltage level (L2). Therefore, themagnitudes of the voltages (VDX1-VDX3) are forced to be substantiallyequal to the second voltage level (L2), the target light emittingelements 4 remain non-conducting, and the voltage across each of thetarget light emitting elements 4 is smaller than but close to theconduction voltage of the target light emitting element 4 in magnitude.It should be noted that the magnitudes of the voltages (VDX1-VDX3) maybe different from each other because of non-ideal effects of the lightemitting array 1 (see FIG. 1).

In the third phase (III) from time t2 to time t4, the enable signal (EN)is at an inactive logic level (e.g., a logic low level) corresponding tonon-conduction of the bias switches 544. With respect to each of thedrive lines 3, when the corresponding pulse width modulation signal(PWM1/PWM2/PWM3) has a duty cycle greater than 0% and smaller than 100%,the third phase (III) is divided into a former portion from time t2 totime t3/t3′/t3″ and a latter portion from time t3/t3′/t3″ to time t4.The third phase (III) has a fixed time span, and the latter portion hasa time span positively correlated to the duty cycle of the correspondingpulse width modulation signal (PWM1/PWM2/PWM3). In the former portion,the control signal (CTRL1/CTRL2/CTRL3) corresponding to the drive line 3is at an active logic level (e.g., a logic high level) corresponding toconduction of the corresponding balance switch 531; the pulse widthmodulation signal (PWM1/PWM2/PWM3) corresponding to the drive line 3 isat the inactive logic level (i.e., the logic low level) corresponding tonon-conduction of the corresponding drive switch 541; and the drive line3 is coupled to the charge balance line 52. In the latter portion, thecontrol signal (CTRL1/CTRL2/CTRL3) corresponding to the drive line 3 isat the inactive logic level (i.e., the logic low level) corresponding tonon-conduction of the corresponding balance switch 531; and the pulsewidth modulation signal (PWM1/PWM2/PWM3) corresponding to the drive line3 is at an active logic level (e.g., a logic high level) correspondingto conduction of the corresponding drive switch 541; and the currentsource 542 corresponding to the drive line 3 provides the correspondingdrive current to the drive line 3. Therefore, the magnitude of thevoltage (VDX1/VDX2/VDX3) at the drive line 3 drops, and thecorresponding target light emitting element 4 becomes conducting.

In an example as shown in FIG. 6 where the duty cycle of each of thepulse width modulation signals (PWM1-PWM3) is greater than 0% andsmaller than 100%, and where the duty cycle of the pulse widthmodulation signal (PWM2) is greater than the duty cycle of the pulsewidth modulation signal (PWM1) and smaller than the duty cycle of thepulse width modulation signal (PWM3), during a period from time t2 totime t3″, magnitude differences among the voltages (VDX1-VDX3) graduallydecrease because of charge sharing among the drive lines 3, and during aperiod from time t3″ to time t3′, the magnitude difference between thevoltages (VDX1, VDX2) gradually decreases because of charge sharingbetween the corresponding drive lines 3. In other words, with respect toeach of the drive lines 3, a period for the drive line 3 to participatein the charge sharing roughly increases with decrease of the duty cycleof the corresponding pulse width modulation signal (PWM1/PWM2/PWM3).

It should be noted that, with respect to each of the drive lines 3, thethird phase (III) would only have the former portion when the duty cycleof the corresponding pulse width modulation signal (PWM) is 0%, andwould only have the latter portion when the duty cycle of thecorresponding pulse width modulation signal (PWM) is 100%.

In an example as shown in FIG. 7 where the duty cycle of each of thepulse width modulation signals (PWM1, PWM2) is greater than 0% andsmaller than 100%, where the duty cycle of the pulse width modulationsignal (PWM2) is greater than the duty cycle of the pulse widthmodulation signal (PWM1), and where the duty cycle of the pulse widthmodulation signal (PWM3) is 100%, during a period from time t2 to timet3′, the magnitude difference between the voltages (VDX1, VDX2)gradually decreases because of charge sharing between the correspondingdrive lines 3, and the magnitude of the voltage (VDX3) remains constantbecause the corresponding drive line 3 does not participate in thecharge sharing.

In the fourth phase (IV) from time t4 to time t5, the enable signal (EN)is at the inactive logic level (i.e., the logic low level) correspondingto non-conduction of the bias switches 544; each of the control signals(CTRL1-CTRL3) is at the inactive logic level (i.e., the logic low level)corresponding to non-conduction of the corresponding balance switch 531;and each of the pulse width modulation signals (PWM1-PWM3) is at theinactive logic level (i.e., the logic low level) corresponding tonon-conduction of the corresponding drive switch 541.

Referring back to FIG. 2, in view of the above, in this embodiment, byvirtue of the charge sharing circuit 53, and by virtue of making atleast two of the balance switches 531 of the charge sharing circuit 53conduct, charge sharing occurs among the drive lines 3 respectivelycorresponding to the conducting balance switches 531, and the magnitudedifference (s) among the voltages respectively at the drive lines 3decrease(s), thereby alleviating the drawback of the prior art.

In the description above, for the purposes of explanation, numerousspecific details have been set forth in order to provide a thoroughunderstanding of the embodiment. It will be apparent, however, to oneskilled in the art, that one or more other embodiments may be practicedwithout some of these specific details. It should also be appreciatedthat reference throughout this specification to “one embodiment,” “anembodiment,” an embodiment with an indication of an ordinal number andso forth means that a particular feature, structure, or characteristicmay be included in the practice of the disclosure. It should be furtherappreciated that in the description, various features are sometimesgrouped together in a single embodiment, figure, or description thereoffor the purpose of streamlining the disclosure and aiding in theunderstanding of various inventive aspects.

While the disclosure has been described in connection with what isconsidered the exemplary embodiment, it is understood that thedisclosure is not limited to the disclosed embodiment but is intended tocover various arrangements included within the spirit and scope of thebroadest interpretation so as to encompass all such modifications andequivalent arrangements.

What is claimed is:
 1. A display system comprising: a light emittingarray including a plurality of scan lines, a plurality of drive lines,and a plurality of light emitting elements arranged in a matrix that hasa plurality of rows respectively corresponding to said scan lines and aplurality of columns respectively corresponding to said drive lines,each of said light emitting elements having a first terminal and asecond terminal, with respect to each of said rows, said first terminalsof said light emitting elements in said row being connected to said scanline that corresponds to said row, with respect to each of said columns,said second terminals of said light emitting elements in said columnbeing connected to said drive line that corresponds to said column; anda driving device including a controller generating a control output, acharge balance line, and a charge sharing circuit coupled to said drivelines, said charge balance line and said controller, and receiving thecontrol output from said controller, with respect to each of said drivelines, said charge sharing circuit being operable, based on the controloutput, to establish or not establish an electrical connection betweensaid drive line and said charge balance line.
 2. The display system ofclaim 1, wherein: the control output includes a control signal; saidcharge sharing circuit includes a plurality of balance switchesrespectively corresponding to said drive lines; and with respect to eachof said drive lines, said balance switch corresponding to said driveline is coupled between said drive line and said charge balance line, isfurther coupled to said controller to receive the control signal, andswitches between conduction and non-conduction based on the controlsignal.
 3. The display system of claim 2, wherein said driving devicefurther includes: a driver coupled to said drive lines, to receive apulse width modulation signal, and operable, based on the pulse widthmodulation signal, to provide or not to provide respectively to saiddrive lines a plurality of drive currents respectively corresponding tosaid drive lines.
 4. The display system of claim 3, wherein: said driver(54) includes a plurality of drive switches respectively correspondingto said drive lines, and a plurality of current sources respectivelycorresponding to said drive lines; and with respect to each of saiddrive lines, said drive switch corresponding to said drive line and saidcurrent source corresponding to said drive line are coupled in seriesbetween said drive line and ground, said drive switch corresponding tosaid drive line is to receive the pulse width modulation signal, andswitches between conduction and non-conduction based on the pulse widthmodulation signal, and when said drive switch corresponding to saiddrive line conducts, said current source corresponding to said driveline provides to said drive line the drive current corresponding to saiddrive line.
 5. The display system of claim 3, wherein said driverfurther includes: a bias circuit coupled to said drive lines, to receivean enable signal, and operable, based on the enable signal, to provideor not to provide respectively to said drive lines a plurality of biasvoltages respectively corresponding to said drive lines.
 6. The displaysystem of claim 5, wherein: said bias circuit includes a plurality ofbias switches respectively corresponding to said drive lines, and aplurality of voltage sources respectively corresponding to said drivelines; and with respect to each of said drive lines, said bias switchcorresponding to said drive line is coupled between said drive line andsaid voltage source corresponding to said drive line, is to receive theenable signal, and switches between conduction and non-conduction basedon the enable signal, and when said bias switch corresponding to saiddrive line conducts, said voltage source corresponding to said driveline provides to said drive line the bias voltage corresponding to saiddrive line.
 7. The display system of claim 1, wherein: the controloutput includes a plurality of control signals respectivelycorresponding to said drive lines; said charge sharing circuit includesa plurality of balance switches; and with respect to each of said drivelines, said balance switch corresponding to said drive line is coupledbetween said drive line and said charge balance line, is further coupledto said controller to receive the control signal corresponding to saiddrive line, and switches between conduction and non-conduction based onthe control signal corresponding to said drive line.
 8. The displaysystem of claim 7, wherein said driving device further includes: adriver coupled to said drive lines, and to receive a plurality of pulsewidth modulation signals respectively corresponding to said drive lines;with respect to each of said drive lines, said driver being operable,based on the pulse width modulation signal corresponding to said driveline, to provide or not to provide to said drive line a drive currentcorresponding to said drive line.
 9. The display system of claim 8,wherein: said driver includes a plurality of drive switches respectivelycorresponding to said drive lines, and a plurality of current sourcesrespectively corresponding to said drive lines; and with respect to eachof said drive lines, said drive switch corresponding to said drive lineand said current source corresponding to said drive line are coupled inseries between said drive line and ground, said drive switchcorresponding to said drive line is to receive the pulse widthmodulation signal corresponding to said drive line, and switches betweenconduction and non-conduction based on the pulse width modulation signalcorresponding to said drive line, and when said drive switchcorresponding to said drive line conducts, said current sourcecorresponding to said drive line provides to said drive line the drivecurrent corresponding to said drive line.
 10. The display system ofclaim 1, wherein said driving device further includes: a scan selectorcoupled to said scan lines, to receive an input voltage, and outputtingthe input voltage to said scan lines sequentially without overlapping intime.
 11. The display system of claim 1, wherein each of said lightemitting elements is a light emitting diode having an anode and acathode that respectively serve as said first terminal and said secondterminal of said light emitting element.
 12. A driving deviceoperatively associated with a light emitting array, the light emittingarray including a plurality of scan lines, a plurality of drive linesand a plurality of light emitting elements, the light emitting elementsbeing arranged in a matrix that has a plurality of rows respectivelycorresponding to the scan lines and a plurality of columns respectivelycorresponding to the drive lines, each of the light emitting elementshaving a first terminal and a second terminal, wherein with respect toeach of the rows, the first terminals of the light emitting elements inthe row are connected to the scan line corresponding to the row, andwith respect to each of the columns, the second terminals of the lightemitting elements in the column are connected to the drive linecorresponding to the column, said driving device comprising: acontroller generating a control output; a charge balance line; and acharge sharing circuit adapted to be coupled to said drive lines,further coupled to said charge balance line and said controller, andreceiving the control output from said controller; with respect to eachof the drive lines, said charge sharing circuit being operable, based onthe control output, to establish or not establish an electricalconnection between the drive line and said charge balance line.